The Phase 10 report continues the accumulation of reliability statistics and research into the fundamental physics of failure in GaN devices.
The company has developed several new reliability tests for the devices, with one for the reliability of eGaN FETs under hard and soft switching conditions at high input voltages (VIN). Using a novel test system developed at EPC, the RDS(on) of parts operating in switching conditions can be measured and this can extrapolate any increases in RDS(on) (also called “dynamic RDS(on)” ) over 10 years of continuous operation. The switching reliability is measured against three acceleration factors: (1) VIN , (2) temperature and, (3) switching frequency.
Recently, the JEDEC JC-70.1 committee released a test guideline for the measurement of dynamic on-resistance (dRDS(on)) in GaN based power electronics. This uses double-pulse inductive hard-switching and EPC uses this to characterize eGaN FETs. But EPC has also developed an extensive resistive hard-switching test capability, which was specifically designed to characterize dRDS(on) over long term continuous hard and/or soft-switching operation. Figure 1 above shows the basic test circuit for this system, based based on a resistive switching circuit where the Device Under Test (DUT) is hard-switched continuously while measuring and logging RDS(on).
The system configuration consists of a motherboard holding the components on Figure 1, except for the DUT, which is mounted on a separate DUT card that plugs into an edge card connector located on the motherboard. An external gate resistor (RG, ext) is used to slow down the switching transients. The purpose of this resistor is twofold: first to minimize gate voltage overshoot (a consequence of the test configuration and its parasitic inductance), and second to enhance the time with simultaneous high voltage and high current present during hard-switching transitions (accelerating potential dRDS(on) effects).
Expanding upon the gate reliability studies in the previous Phase 6 report, EPC also developed new test hardware that allows populations of parts to be tested under DC gate