Checking that all JTAG-enabled devices in a scan chain are connected correctly is normally a manual process and therefore just as susceptible to human error as any other manual design process. But it has recently become possible to automate the design verification of a boundary scan chain. Using its expertise in boundary scan testing, XJTAG has developed a free software extension for Altium Designer that assists with the design verification of a boundary scan chain, enabling a new level of DFT capability to the environment.
The extension, called XJTAG DFT Assistant, uses the netlist generated by Altium Designer during schematic capture to form a profile of how the scan chain is connected in the design. This picture is complemented by importing BSDL files to the project, allowing it to understand how the scan chain should be routed. From here the extension is able to not only check the connections of the scan chain in the schematic but also show the level of test access the design offers to boundary scan software/hardware.
The extension achieves this through two main features; the XJTAG Chain Checker and the XJTAG Access Viewer. The data collated can also be exported for use in XJTAG’s boundary scan test development environment, XJDeveloper. This supports the development of boundary scan tests for both JTAG-enabled and non JTAG-enabled devices. It is possible to extend test access to a larger percentage of the circuit if it is designed with boundary scan testability in mind. Using the XJTAG Access Viewer feature, designers can monitor, evaluate and maximise their test access at the schematic capture stage, something that couldn’t be automatically verified before the introduction of this free software extension.
Crucially, the extension is also able to detect errors in the scan chain long before the PCB moves to the layout stage. By making it part of the design process, the XJTAG DFT Assistant can help designers avoid the common faults that would normally inhibit a scan chain from working, such as incorrectly routed TAP signals or poorly terminated signals. Perhaps more importantly, it shows the board designer which ICs are accessible to boundary scan testing, thereby highlighting any ICs that should be connected and aren’t, or areas of a design that are currently inaccessible to boundary scan testing but could be, by making some design changes.
These features can be used iteratively as the design evolves, ensuring that test access is maximised and that the boundary scan chains are right by design. Having this information at their fingertips will not only make developers more aware of how to implement boundary scan, but help automate the entire DFT approach to schematic design.
Understanding boundary scan and BSDL files enables specialists like XJTAG to develop the software and hardware products needed to use boundary scan throughout a product’s life-cycle, from prototype bring-up to volume production. By applying this expertise to develop a free software extension for Altium Designer, developers now have access to a powerful design verification technology that greatly increases their ability to get it right first time.
About the author:
Philip Ling is Technical Marketing Manager at XJTAG - www.xjtag.com/altium