Making design-for-test a push-button process: Page 2 of 3

March 02, 2016 //By Philip Ling
Making design-for-test a push-button process
Implementing a Design for Test approach when designing PCBs at the schematic capture stage can now be significantly assisted using an innovative and free software extension that adds design verification to Altium Designer.

Getting the scan chain correct

Boundary scan is implemented using a dedicated bus, which comprises between four and five signals. These signals, collectively referred to as a Test Access Port, or TAP, need to be correctly connected to all JTAG-enabled ICs in a daisy-chain configuration, known as a scan chain. The TAP is routed from a connector to the first IC in the scan chain and then on to the next and so on, all the way to the last IC in the chain and back to the connector.

The sequential nature of the scan chain means that the boundary scan test pattern must pass through each device and return to the connector. It is therefore imperative that there are no broken or weak links in the scan chain. This introduces a number of DFT considerations, such as ensuring the scan chain is connected to every JTAG-enabled IC in the design, that the chain’s TAP signals are correctly connected to the right pins on those ICs and that the recommended termination is used on the TAP signals.

Fig. 1: The boundary scan chain sequentially connects JTAG-enabled devices on a PCB, enabling test access for running connectivity and functional tests.

As well as defining the electrical characteristics of the TAP, the IEEE 1149.1 (boundary scan) standard defines the scan chain’s protocol. This enables the identification of devices, the pins used for the TAP and the test capabilities that device supports. This information is stored in a dedicated file known as the Boundary Scan Description Language file (BSDL); every IC that is JTAG-compliant must have a BSDL file associated with it. The information held in this file enables specialist software and hardware providers to create the products used to access and control JTAG-enabled devices during test.

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