Flexible instruments for HDMI and DisplayPort test

October 29, 2019 //By Nick Flaherty
Teledyne LeCroy's quantumdata M41h (HDMI) and M41d (DisplayPort) test systems can be upgraded from functional testers to protocol analysers
Teledyne LeCroy's quantumdata M41h HDMI and M41d DisplayPort test systems can be upgraded from functional testers to protocol analysers

Teledyne LeCroy has launched flexible HDMI 2.1 and DisplayPort test systems for or video designers and integrators providing functional to full protocol compliance testing.

The quantumdata M41h HDMI and M41d DisplayPort test instruments allow design and test engineers to test and validate their products for interoperability and reliability of the HDMI 2.1 or DisplayPort 1.4 video interface implementations. More functionality an be added via software licenses as additional requirements arise.

The quantumdata M41h and M41d can be upgraded from a functional tester with source and sink to a protocol analyser and, if desired, can test full standards compliance, enabling developers to pre-test or self-test independently, reducing delays and costs. 

The M41h equipped with both an HDMI Tx port and an HDMI Rx port for testing FRL-capable and TMDS sources and sinks up to aggregate data rates of 48Gb/s. The M41h is also supports enhanced Audio Return Channel (eARC) Tx/Rx functional testing and compliance testing or both eARC Tx devices and eARC Rx devices.

The HDMI Rx port provides deep analysis capabilities for HDMI 2.1 Fixed Rate Link (FRL) with  Forward Error Correction (FEC) up to 48Gbps (12Gbps/Channel). The HDMI Rx analyzer port provides visibility into the Fixed Rate Link packetization—FRL packets, Character blocks and Super blocks. The instrument also supports analysis of the FRL link training functions of a receiver in the FRL mode in both 3 lane and 4 lane configurations to test a source's FRL link training function. Deep analysis of FRL source streams or TMDS streams enables you to identify and resolve interoperability problems early in the product life cycle. The M41h depicts the incoming FRL packet structure and associated control elements. This includes depicting the Character Block structure and Super Block structure. All FRL packet data elements are assigned precise timestamps. Once the FRL stream is captured you can view and analyze the underlying TMDS (tri-byte) contents as well.

Next: DisplayPort test


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