The SATA specification defines a data rate of 6 Gbit/sec. 8b/10b encoding of the transmitted data leads to a 20% overhead that is not used for user data. The protocol also requires extra bandwidth to compress the data into the FIS (Frame Information Structure). The underlying assumption is that all data is transmitted without errors. To detect individual errors and to verify the transmission, the SATA specification defines a CRC (Cyclic Redundancy Check) error detection code. While CRC is very efficient, it can only detect errors, it cannot repair them. So, if an error occurs, the data transmission has to be restarted.
To prevent the data transmission from needing to restart, the specification defines clear attributes for the signals. For instance, the signal frequency on the circuit board and the connector is specified at 3 GHz (6 Gbit/sec). At these frequencies, PCB routing must follow specific rules. But, it is no longer enough to simply follow high speed routing rules. Various tricks are applied on the chips to optimise the transfer and the behaviour of the controller modules also needs to be aligned with the routing. On the driver side, pre-emphasis - a kind of signal pre-distortion – is used to compensate for the characteristics of the transmission line from transmitter to receiver. A typical SATA transmission line consists of the PCB routing, at least two connectors and a cable. This line forms an RC combination that acts primarily as a low-pass filter. However, the exact properties of the filter vary from system to system. By adjusting the strength of driver and pre-emphasis, it is possible to align chips and system. The driver strength also influences the absolute signal strength, while pre-emphasis adjusts the strength for non-transition bits, i.e. bits that do not follow a transition.
PCIe Gen3 provides a complex algorithm that lets the transmitter and receiver negotiate the best settings. The SATA specification is not as