All you wanted to know about high-performance timing in Board design

November 05, 2013 //By Ian Dobson
All you wanted to know about high-performance timing in Board design
Ian Dobson of IDT considers the options facing board designers when working with high-performance timing.

Being a board designer is a tough job (that’s why this author went into management as soon as the opportunity presented itself).  Performing all the necessary tasks to generate the full schematic and guide its implementation requires finding the right trade-offs amongst a plethora of competing needs.

  • The Marketing team is demanding a set of features that will barely fit inside the Vehicle Assembly Building at Cape Kennedy, while the Mechanical Design team has allocated a matchbook-sized cubby hole just behind the corporate logo for your board.
  • The CTO Office is suggesting some technology they saw in a science-fiction movie last week, while the Purchasing team is insisting you can only use components already on an “Approved Parts List” that is three-quarters vacuum tubes. 
  • The Software team is refusing to consider a new processor since that might require them to port their code.  However their request for 8x the RAM of the last design makes you suspect there’s a performance problem coming your way when this all hits the lab. 
  • The Power Group has managed to give you an extra 200W of power, but only by giving it to you at 120VAC so that converting it to the needed voltages will count against your thermal budget, not theirs.
  • And speaking of thermal budgets, you’ve been asked to make do with 20% less than the last design and the air flow will already be at 75°C by the time it gets to your board. 

The last thing you need is to scan the datasheet for the PHY chip you’ve finally got everyone to agree on and see a 3-page table defining its reference clock specifications.  A reference clock specification should have frequency and maybe duty cycle.  That’s all.  It better, because your manager only allowed you 2 days before the final schematic review to get the whole clock tree selected and added.

As most board designers are aware, clock component selection

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